1. Technical Field
The present invention relates to a variable-gain amplifier.
2. Related Art
Latest progress in fine gate processing technique has made it possible to apply a CMOS transistor to a GHz RF band, thereby fabricating a wireless system IC including a single chip, through a CMOS process that can integrate a RF-IC and a baseband-IC.
FIG. 11 is a block diagram showing a system configuration of a popular wireless communication terminal. The system includes variable-gain amplifiers at some key points, for absorbing gain fluctuation in a transmitting circuit and a receiving circuit, and adjusting and securing the total gain. Regarding the first-stage amplifier in the receiving circuit in particular, when a signal output from the antenna is weak the amplifier has to have a low-noise and high-gain characteristic for amplifying the signal, and when the signal output from the antenna is intense the amplifier has to have a high linearity in a low gain range, for attenuating the signal. Especially for preventing degradation of a desired wave by a disturbance wave having high signal intensity, such as an adjacent channel disturbance wave, a second adjacent channel disturbance wave or an in-band blocker, strict communication standards are generally provided. Thus, the amplifier employed at the first stage of the receiving circuit is required to provide wide variable range, low noise and high linearity at the same time.
FIG. 12 is a circuit diagram of a variable-gain amplifier disclosed in Japanese Laid-open patent publication No. 2005-136846. This amplifier includes three bipolar transistors Q1, Q2, Q3 that amplify a signal, and a base current control circuit 201. The collector of each transistor Q1, Q2, Q3 is connected to an output terminal “Output”, as well as to an end of a resistor RL, which is a common load resistance. The other end of the resistor RL is connected to a power supply line Vcc to which a source voltage is applied. An input terminal “Input” is connected to the base of the transistor Q1 via a capacitor Csr1. The input terminal “Input” is also connected to the base of the transistor Q2, via the capacitor Csr1 and an attenuator AT1 which serves to attenuate an input signal.
The attenuator AT1 includes a capacitor Csr2 serially connected to the base of the transistor Q1, and a capacitor Csh2. The capacitor Csh2 is shunt-connected between a signal path posterior to the capacitor Csr2 (signal path connecting the capacitor Csr2 and the base of the transistor Q2) and the ground. Likewise, the input terminal “Input” is connected to the base of the transistor Q3 via the capacitor Csr1, the attenuator AT1 and an attenuator AT2 serving to attenuate the input signal. The attenuator AT2 includes a capacitor Csr3 serially connected to the base of the transistor Q2, and a capacitor Csh3. The capacitor Csh3 is shunt-connected between a signal path posterior to the capacitor Csr3 (signal path connecting the capacitor Csr3 and the base of the transistor Q3) and the ground.
With such structure, the variable amplifier allows switching between the unit amplifier, and the plurality of attenuators connected in parallel between the signal input terminal and the signal output terminal, and thereby varying the gain and linearity of the variable amplifier as a whole. The number of switch stages may be determined as desired if not fewer than two, and the example of FIG. 12 has three stages.
FIG. 13 is a circuit diagram of the base current control circuit 201 shown in FIG. 12. Referring to FIG. 13, working principle of the circuit of FIG. 12 will be described. With changes of the control voltage Vctrl, the variable-gain amplifier works as follows. While the control voltage Vctrl is sufficiently higher than reference voltages Vr1, Vr2, the transistor Qb2 and the transistor Qb4 of the base current control circuit 201 are turned off. Accordingly, an entirety of a total base current determined by a current mirror circuit for setting the total current is supplied to the base of the transistor Q1 of the amplifier, via the transistor Qb1. The remaining transistors Q2, Q3, are, therefore, turned off.
Under such state, the transistor Q1 receives the signal input to the input terminal “Input” without mediation of the attenuator. Accordingly the gain becomes maximal, and IIP3, which is an index of the linearity of the variable amplifier as a whole, reflects the linearity of the transistor Q1 itself as it is.
As the control voltage Vctrl becomes lower, a part of the current supplied to the base of the transistor Q1 starts to be supplied to the base of the transistor Q2. In other words, with the drop of the control voltage Vctrl, the base current of the transistor Q1 gradually decreases, while the base current of the transistor Q2 gradually increases. Accordingly, transistor Q1 gradually loses the gain with the decrease in collector current. In contrast, the transistor Q2 obtains higher gain with the increase in collector current. As already stated, the gain of the signal path through the transistor Q2 is lower than that of the signal path through the transistor Q1 provided that the base current is equal, and hence the overall gain of the variable amplifier decreases (Ref. FIG. 4 of Japanese Laid-open patent publication No. 2005-136846).
Also as already stated, the signal path through the transistor Q2 has higher linearity than the signal path through the transistor Q1 provided that the base current is equal, and accordingly the overall linearity of the variable amplifier increases. When the control voltage Vctrl becomes still lower, the increase in collector current of the transistor Q2 increases the gain of the transistor Q2, thereby nearly turning off the transistor Q1. Since the input of the transistor Q2 is made via the attenuator AT1 the overall gain of the variable amplifier becomes lower in this case, and the IIP3 of the variable amplifier as a whole presents a value obtained by summing the characteristic of the transistor Q2 itself and the attenuation factor expressed in decibel (dB).
When the control voltage Vctrl drops even further, the transistor Qb1 and the transistor Qb3 are turned off. Accordingly, the entirety of the total base current set by the resistor Rref and the transistors Qref/Qbcs of the base current control circuit 201 is supplied to the base of the transistor Q3 via the transistor Qb1, an the remaining transistors Q1, Q2 are both turned off. Under such state, the signal input to the input terminal “Input” is provided to the transistor Q3 via the attenuators AT1, AT2, and therefore the overall gain of the variable amplifier becomes minimal, while the IIP3 of the variable amplifier as a whole becomes highest.
In the variable-gain amplifier, a sufficient isolation characteristic has to be secured between the input terminal and the output terminal. The amount of isolation of the input/output (hereinafter, I/O) terminal of the first-stage unit amplifier (transistor Q1 in FIG. 12) determines how much attenuation range can be secured. For example, it will be assumed that the amount of isolation between base and collector of the transistor Q1 in FIG. 12 is −20 dB at the frequency of 1 GHz, while a minimum gain of the variable-gain amplifier to be achieved by the combination of the attenuator and the unit amplifier is −30 dB. In this case, since the amount of I/O isolation of the transistor Q1 is −20 dB at 1 GHz, the minimum gain cannot be lowered to −30 dB, but instead determined around −20 dB, which is the amount of isolation of the transistor Q1. Thus, in order to secure a sufficient attenuation range, it is essential to secure the matching amount of I/O isolation of the first-stage unit amplifier.
FIG. 14 is a circuit diagram of another variable-gain amplifier disclosed in Japanese Laid-open patent publication No. 2005-136846. FIG. 15 is a graph for comparing control voltage dependence of the gain and the IIP3 characteristic of the amplifier of FIG. 14. Performing thus a multi-stage cascode connection enables attaining higher isolation. However, because of employing bipolar transistors, which have to be vertically stacked, effective operation cannot be performed unless the source voltage is increased. Consequently, such structure does not provide a sufficient characteristic.